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1 LTC3707 3707f high efficiency, 2-phase synchronous step-down switching regulator figure 1. high efficiency dual 5v/3.3v step-down converter n 180 phased dual controllers reduce required input capacitance and power supply induced noise n opti-loop ? compensation minimizes c out n 1.5% output voltage accuracy over temperature n dual n-channel mosfet synchronous drive n power good output voltage monitor n dc programmed fixed frequency 150khz to 300khz n wide v in range: 4.5v to 28v operation n very low dropout operation: 99% duty cycle n adjustable soft-start current ramping n foldback output current limiting n latched short-circuit shutdown with defeat option n output overvoltage protection n remote output voltage sense n low shutdown i q : 20 m a n 5v and 3.3v standby regulators n small 28-lead narrow ssop package n selectable constant frequency, burst mode ? operation or pwm operation the ltc ? 3707 is a high performance dual step-down switching regulator controller that drives n-channel syn- chronous power mosfet stages. a constant frequency current mode architecture allows adjustment of the fre- quency up to 300khz. power loss and noise due to the esr of the input capacitors are minimized by operating the two controller output stages out of phase. opti-loop compensation allows the transient response to be optimized over a wide range of output capacitance and esr values. the precision 0.8v reference and power good output indicator are compatible with future microproces- sor generations, and a wide 3.5v to 30v input supply range encompasses all battery chemistries. a run/ss pin for each controller provides both soft-start and optional timed, short-circuit shutdown. current foldback limits mosfet dissipation during short-circuit conditions when overcurrent latchoff is disabled. output overvoltage protection circuitry latches on the bottom mosfet until v out returns to normal. the fcb mode pin can select among burst mode operation, constant fre- quency mode and continuous inductor current mode or regulate a secondary winding. n notebook and palmtop computers, pdas n battery chargers n portable instruments n battery-operated digital devices n dc power distribution systems , ltc and lt are registered trademarks of linear technology corporation. burst mode and opti-loop are registered trademarks of linear technology corporation. descriptio u features applicatio s u typical applicatio u + 4.7 f d3 d4 d1 m2 m1 c b1 , 0.1 f r2 105k 1% 1000pf l1 6.3 h c c1 220pf 1 f ceramic c in 22 f 50v ceramic + c out1 47 f 6v sp r sense1 0.01 r1 20k 1% r c1 15k v out1 5v 5a d2 m4 m3 c b2 , 0.1 f r4 63.4k 1% l2 6.3 h c c2 220pf 1000pf + c out 56 f 6v sp r sense2 0.01 r3 20k 1% r c2 15k v out2 3.3v 5a tg1 tg2 boost1 boost2 sw1 sw2 bg1 bg2 sgnd pgnd sense1 + sense2 + sense1 sense2 v osense1 v osense2 i th1 i th2 v in intv cc run/ss1 run/ss2 v in 5.2v to 28v m1, m2, m3, m4: fds6680a 3707 f01 c ss1 0.1 f c ss2 0.1 f LTC3707
2 LTC3707 3707f order part number LTC3707egn (note 1) input supply voltage (v in ).........................30v to C 0.3v top side driver voltages (boost1, boost2) ...................................36v to C 0.3v switch voltage (sw1, sw2) .........................30v to C 5v intv cc, extv cc , run/ss1, run/ss2, (boost1-sw1), (boost2-sw2), pgood .............................7v to C 0.3v sense1 + , sense2 + , sense1 C , sense2 C voltages ........................ (1.1)intv cc to C 0.3v freqset, stbymd, fcb voltage ........ intv cc to C 0.3v i th1, i th2 , v osense1 , v osense2 voltages ... 2.7v to C 0.3v peak output current <10 m s (tg1, tg2, bg1, bg2) ... 3a intv cc peak output current ................................ 40ma operating temperature range LTC3707eg (note 2) .......................... C 40 c to 85 c junction temperature (note 3) ............................. 125 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c t jmax = 125 c, q ja = 95 c/w the l denotes the specifications which apply over the full operating symbol parameter conditions min typ max units main control loops v osense1, 2 regulated feedback voltage (note 4); i th1, 2 voltage = 1.2v l 0.788 0.800 0.812 v i vosense1, 2 feedback current (note 4) C 5 C 50 na v reflnreg reference voltage line regulation v in = 3.6v to 30v (note 4) 0.002 0.02 %/v v loadreg output voltage load regulation (note 4) measured in servo loop; d i th voltage = 1.2v to 0.7v l 0.1 0.5 % measured in servo loop; d i th voltage = 1.2v to 2.0v l C 0.1 C 0.5 % g m1, 2 transconductance amplifier g m i th1, 2 = 1.2v; sink/source 5ua; (note 4) 1.3 mmho g mgbw1, 2 transconductance amplifier gbw i th1, 2 = 1.2v; (note 4) 3 mhz i q input dc supply current (note 5) normal mode extv cc tied to v out1 ; v out1 = 5v 350 m a standby v run/ss1, 2 = 0v, v stbymd > 2v 125 m a shutdown v run/ss1, 2 = 0v, v stbymd = open 20 35 m a v fcb forced continuous threshold l 0.76 0.800 0.84 v i fcb forced continuous pin current v fcb = 0.85v C 0.30 C 0.18 C 0.1 m a v binhibit burst inhibit (constant frequency) measured at fcb pin 4.3 4.8 v threshold uvlo undervoltage lockout v in ramping down l 3.5 4 v v ovl feedback overvoltage lockout measured at v osense1, 2 l 0.84 0.86 0.88 v i sense sense pins total source current (each channel); v sense1 C , 2 C = v sense1 + , 2 + = 0v C 90 C 60 m a v stbymd ms master shutdown threshold v stbymd ramping down 0.4 0.6 v temperature range, otherwise specifications are at t a = 25 c. v in = 15v, v run/ss1, 2 = 5v unless otherwise noted. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 top view gn package 28-lead plastic ssop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 run/ss1 sense1 + sense1 v osense1 freqset stbymd fcb i th1 sgnd 3.3v out i th2 v osense2 sense2 sense2 + pgood tg1 sw1 boost1 v in bg1 extv cc intv cc pgnd bg2 boost2 sw2 tg2 run/ss2 absolute axi u rati gs w ww u package/order i for atio uu w electrical characteristics consult ltc marketing for parts specified with wider operating temperature ranges.
3 LTC3707 3707f the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 15v, v run/ss1, 2 = 5v unless otherwise noted. electrical characteristics symbol parameter conditions min typ max units v stbymd ka keep-alive power on-threshold v stbymd ramping up, run ss1, 2 = 0v 1.5 2 v df max maximum duty factor in dropout 98 99.4 % i run/ss1, 2 soft-start charge current v run/ss1, 2 = 1.9v 0.5 1.2 m a v run/ss1, 2 on run/ss pin on threshold v run/ss1, v run/ss2 rising 1.0 1.5 2.0 v v run/ss1, 2 lt run/ss pin latchoff arming threshold v run/ss1, v run/ss2 rising from 3v 4.1 4.75 v i scl1, 2 run/ss discharge current soft short condition v osense1, 2 = 0.5v; 0.5 2 4 m a v run/ss1, 2 = 4.5v i sdlho shutdown latch disable current v osense1, 2 = 0.5v 1.6 5 m a v sense(max) maximum current sense threshold v osense1, 2 = 0.7v,v sense1 C , 2 C = 5v 65 75 85 mv l 62 75 88 mv tg transition time: (note 6) tg1, 2 t r rise time c load = 3300pf 60 110 ns tg1, 2 t f fall time c load = 3300pf 60 110 ns bg transition time: (note 6) bg1, 2 t r rise time c load = 3300pf 50 110 ns bg1, 2 t f fall time c load = 3300pf 50 100 ns tg/bg t 1d top gate off to bottom gate on delay synchronous switch-on delay time c load = 3300pf each driver 80 ns bg/tg t 2d bottom gate off to top gate on delay top switch-on delay time c load = 3300pf each driver 80 ns t on(min) minimum on-time tested with a square wave (note 7) 180 ns intv cc linear regulator v intvcc internal v cc voltage 6v < v in < 30v, v extvcc = 4v 4.8 5.0 5.2 v v ldo int intv cc load regulation i cc = 0 to 20ma, v extvcc = 4v 0.2 2.0 % v ldo ext extv cc voltage drop i cc = 20ma, v extvcc = 5v 100 200 mv v extvcc extv cc switchover voltage i cc = 20ma, extv cc ramping positive l 4.5 4.7 v v ldohys extv cc hysteresis 0.2 v oscillator f osc oscillator frequency v freqset = open (note 8) 190 220 250 khz f low lowest frequency v freqset = 0v 120 140 160 khz f high highest frequency v freqset = 2.4v 280 310 360 khz i freqset freqset input current v freqset = 0v C 2 C 1 m a 3.3v linear regulator v 3.3out 3.3v regulator output voltage no load l 3.20 3.35 3.45 v v 3.3il 3.3v regulator load regulation i 3.3 = 0 to 10ma 0.5 2 % v 3.3vl 3.3v regulator line regulation 6v < v in < 30v 0.05 0.2 % pgood output v pgl pgood voltage low i pgood = 2ma 0.1 0.3 v i pgood pgood leakage current v pgood = 5v 1 m a v pg pgood trip level, either controller v osense respect to set output voltage v osense ramping negative C 6 C7.5 C 9.5 % v osense ramping positive 6 7.5 9.5 %
4 LTC3707 3707f note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: the LTC3707e is guaranteed to meet performance specifications from 0 c to 70 c. specifications over the C 40 c to 85 c operating temperature range are assured by design, characterization and correlation with statistical process controls. note 3: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formula: LTC3707egn = t j = t a + (p d ? 85 c/w) note 4: the LTC3707 is tested in a feedback loop that servos v ith1, 2 to a specified voltage and measures the resultant v osense1, 2. note 5: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. see applications information. note 6: rise and fall times are measured using 10% and 90% levels. delay times are measured using 50% levels. note 7: the minimum on-time condition is specified for an inductor peak-to-peak ripple current 3 40% of i max (see minimum on-time considerations in the applications information section). note 8: v freqset pin internally tied to a 1.19v reference through a large resistance. efficiency vs output current and mode (figure 13) output current (a) 0.001 0 efficiency (%) 10 30 40 50 100 70 0.01 0.1 1 3707 g01 20 80 90 60 10 forced continuous mode (pwm) constant frequency (burst disable) burst mode operation v in = 15v v out = 5v output current (a) 0.001 efficiency (%) 70 80 10 3707 g02 60 50 0.01 0.1 1 100 90 v in = 10v v in = 15v v in = 7v v in = 20v v in = 15v v out = 5v input voltage (v) 5 efficiency (%) 70 80 3707 g03 60 50 15 25 30 100 v out = 5v i out = 3a 90 efficiency vs output current (figure 13) efficiency vs input voltage (figure 13) intv cc and extv cc switch voltage vs temperature supply current vs input voltage and mode (figure 13) input voltage (v) 05 0 supply current ( a) 400 1000 10 20 25 3707 g04 200 800 600 15 30 both controllers on standby shutdown extv cc voltage drop current (ma) 0 extv cc voltage drop (mv) 200 150 100 50 0 40 3707 g05 10 20 30 temperature ( c) ?0 intv cc and extv cc switch voltage (v) 4.95 5.00 5.05 25 75 3707 g06 4.90 4.85 ?5 0 50 100 125 4.80 4.70 4.75 intv cc voltage extv cc switchover threshold electrical characteristics typical perfor a ce characteristics uw
5 LTC3707 3707f internal 5v ldo line reg maximum current sense threshold vs duty factor maximum current sense threshold vs percent of nominal output voltage (foldback) input voltage (v) 0 4.8 4.9 5.1 15 25 3707 g07 4.7 4.6 510 20 30 4.5 4.4 5.0 intv cc voltage (v) i load = 1ma duty factor (%) 0 0 v sense (mv) 25 50 75 20 40 60 80 3707 g08 100 percent on nominal output voltage (%) 0 v sense (mv) 40 50 60 100 3707 g09 30 20 0 25 50 75 10 80 70 maximum current sense threshold vs v run/ss (soft-start) v run/ss (v) 0 0 v sense (mv) 20 40 60 80 1234 3707 g10 56 v sense(cm) = 1.6v maximum current sense threshold vs sense common mode voltage common mode voltage (v) 0 v sense (mv) 72 76 80 4 3707 g11 68 64 60 1 2 3 5 current sense threshold vs i th voltage v ith (v) 0 v sense (mv) 30 50 70 90 2 3707 g12 10 ?0 20 40 60 80 0 ?0 ?0 0.5 1 1.5 2.5 load regulation load current (a) 0 normalized v out (%) 0.2 0.1 4 3707 g13 0.3 0.4 1 2 3 5 0.0 fcb = 0v v in = 15v figure 1 v ith vs v run/ss v run/ss (v) 0 0 v ith (v) 0.5 1.0 1.5 2.0 2.5 1 234 3707 g14 56 v osense = 0.7v sense pins total source current v sense common mode voltage (v) 0 i sense ( a) 0 3707 g15 ?0 100 24 50 100 6 typical perfor a ce characteristics uw
6 LTC3707 3707f temperature ( c) 50 ?5 70 v sense (mv) 74 80 0 50 75 3707 g17 72 78 76 25 100 125 output current (a) 0 0 dropout voltage (v) 1 2 3 4 0.5 1.0 1.5 2.0 3707 g18 2.5 3.0 3.5 4.0 r sense = 0.015 r sense = 0.010 v out = 5v maximum current sense threshold vs temperature dropout voltage vs output current (figure 13) soft-start up (figure 13) v out 5v/div v run/ss 5v/div i out 2a/div v in = 15v 5ms/div 3707 g19 v out = 5v load step (figure 13) v out 200mv/div i out 2a/div v in = 15v 20 m s/div 3707 g20 v out = 5v load step = 0a to 3a burst mode operation load step (figure 13) v out 200mv/div i out 2a/div v in = 15v 20 m s/div 3707 g21 v out = 5v load step = 0a to 3a continuous mode input source/capacitor instantaneous current (figure 13) i in 2a/div v in 200mv/div v sw1 10v/div v in = 15v 1 m s/div 3707 g22 v out = 5v i out5 = i out3.3 = 2a burst mode operation (figure 13) v out 20mv/div i out 0.5a/div v in = 15v 10 m s/div 3707 g23 v out = 5v v fcb = open i out = 20ma constant frequency (burst inhibit) operation (figure 13) v out 20mv/div i out 0.5a/div v in = 15v 2 m s/div 3707 g24 v out = 5v v fcb = 5v i out = 20ma v sw2 10v/div run/ss current vs temperature temperature ( c) ?0 25 0 run/ss current ( a) 0.2 0.6 0.8 1.0 75 100 50 1.8 3707 g25 0.4 0 25 125 1.2 1.4 1.6 typical perfor a ce characteristics uw
7 LTC3707 3707f current sense pin input current vs temperature extv cc switch resistance vs temperature temperature ( c) ?0 25 25 current sense input current ( a) 29 35 0 50 75 3707 g26 27 33 31 25 100 125 v out = 5v temperature ( c) ?0 25 0 extv cc switch resistance ( ) 4 10 0 50 75 3707 g27 2 8 6 25 100 125 oscillator frequency vs temperature temperature ( c) ?0 200 250 350 25 75 3707 g28 150 100 ?5 0 50 100 125 50 0 300 frequency (khz) v freqset = 5v v freqset = open v freqset = 0v undervoltage lockout vs temperature temperature ( c) ?0 undervoltage lockout (v) 3.40 3.45 3.50 25 75 3707 g29 3.35 3.30 ?5 0 50 100 125 3.25 3.20 shutdown latch thresholds vs temperature temperature ( c) ?0 25 0 shutdown latch thresholds (v) 0.5 1.5 2.0 2.5 75 100 50 4.5 3707 g30 1.0 0 25 125 3.0 3.5 4.0 latch arming latchoff threshold typical perfor a ce characteristics uw
8 LTC3707 3707f run/ss1, run/ss2 (pins 1, 15): combination of soft- start, run control inputs and short-circuit detection timers. a capacitor to ground at each of these pins sets the ramp time to full output current. forcing either of these pins back below 1.0v causes the ic to shut down the circuitry required for that particular controller. latchoff overcurrent protection is also invoked via this pin as described in the applications information section. sense1 + , sense2 + (pins 2, 14): the (+) input to the differential current comparators. the i th pin voltage and controlled offsets between the sense C and sense + pins in conjunction with r sense set the current trip threshold. sense1 C , sense2 C (pins 3, 13): the (C) input to the differential current comparators. v osense1 , v osense2 (pins 4, 12): receives the remotely- sensed feedback voltage for each controller from an external resistive divider across the output. freqset (pin 5): frequency control input to the oscilla- tor. this pin can be left open, tied to ground, tied to intv cc or driven by an external voltage source. this pin can also be used with an external phase detector to build a true phase-locked loop. stbymd (pin 6): control pin that determines which cir- cuitry remains active when the controllers are shut down and/or provides a common control point to shut down both controllers. see the operation section for details. fcb (pin 7): forced continuous control input. this input acts on the first controller (or both controllers depending upon the fltcpl pinsee pin description), and is normally used to regulate a secondary winding. pulling this pin below 0.8v will force continuous synchronous operation for the first and optionally the second control- ler. do not leave this pin floating. i th1, i th2 (pins 8, 11): error amplifier output and switch- ing regulator compensation point. each associated chan- nels current comparator trip point increases with this control voltage. sgnd (pin 9): small signal ground common to both controllers, must be routed separately from high current grounds to the common (C) terminals of the c out capacitors. 3.3v out (pin 10): output of a linear regulator capable of supplying 10ma dc with peak currents as high as 50ma. pgnd (pin 20): driver power ground. connects to the sources of bottom (synchronous) n-channel mosfets, an- odes of the schottky rectifiers and the (C) terminal(s) of c in . intv cc (pin 21): output of the internal 5v linear low dropout regulator and the extv cc switch. the driver and control circuits are powered from this voltage source. must be decoupled to power ground with a minimum of 4.7 m f tantalum or other low esr capacitor. the intv cc regulator standby function is determined by the stbymd pin. extv cc (pin 22): external power input to an internal switch connected to intv cc . this switch closes and supplies v cc power, bypassing the internal low dropout regulator, whenever extv cc is higher than 4.7v. see extv cc connection in applications section. do not exceed 7v on this pin. bg1, bg2 (pins 23, 19): high current gate drives for bottom (synchronous) n-channel mosfets. voltage swing at these pins is from ground to intv cc . v in (pin 24): main supply pin. a bypass capacitor should be tied between this pin and the signal ground pin. boost1, boost2 (pins 25, 18): bootstrapped supplies to the top side floating drivers. capacitors are connected between the boost and switch pins and schottky diodes are tied between the boost and intv cc pins. voltage swing at the boost pins is from intv cc to (v in + intv cc ). sw1, sw2 (pins 26, 17): switch node connections to inductors. voltage swing at these pins is from a schottky diode (external) voltage drop below ground to v in . tg1, tg2 (pins 27, 16): high current gate drives for top n-channel mosfets. these are the outputs of floating drivers with a voltage swing equal to intv cc C 0.5v superimposed on the switch node voltage sw. pgood (pin 28): open-drain logic output. pgood is pulled to ground when the voltage on either v osense pin is not within 7.5% of its set point. uu u pi fu ctio s
9 LTC3707 3707f figure 2 switch logic + 0.8v 4.8v 5v v in 4.5v binh clk2 clk1 0.18 a r6 r5 + fcb + + + + v ref internal supply 3.3v out v sec 3v fcb pgood extv cc intv cc sgnd stbymd + 5v ldo reg sw shdn 0.55v top boost tg c b c in d 1 d b pgnd bot bg intv cc intv cc v in + c sec c out v out 3707 fd/f02 d sec r sense r2 + v osense drop out det run soft- start bot top on s r q q oscillator freqset fcb ea 0.86v 0.80v ov v fb 1.2 a 6v r1 + + 0.74v 0.86v v fb + r c 4(v fb ) rst shdn run/ss i th c c c c2 c ss 1.19v 1m + 4(v fb ) 0.86v slope comp 3mv + + sense sense + intv cc 30k 45k 2.4v 45k 30k i1 i2 b duplicate for second controller channel + + fu ctio al diagra u u w
10 LTC3707 3707f (refer to functional diagram) main control loop the LTC3707 uses a constant frequency, current mode step-down architecture with the two controller channels operating 180 degrees out of phase. during normal opera- tion, each top mosfet is turned on when the clock for that channel sets the rs latch, and turned off when the main current comparator, i 1 , resets the rs latch. the peak inductor current at which i 1 resets the rs latch is con- trolled by the voltage on the i th pin, which is the output of each error amplifier ea. the v osense pin receives the voltage feedback signal, which is compared to the internal reference voltage by the ea. when the load current in- creases, it causes a slight decrease in v osense relative to the 0.8v reference, which in turn causes the i th voltage to increase until the average inductor current matches the new load current. after the top mosfet has turned off, the bottom mosfet is turned on until either the inductor current starts to reverse, as indicated by current compara- tor i 2 , or the beginning of the next cycle. the top mosfet drivers are biased from floating boot- strap capacitor c b , which normally is recharged during each off cycle through an external diode when the top mosfet turns off. as v in decreases to a voltage close to v out , the loop may enter dropout and attempt to turn on the top mosfet continuously. the dropout detector de- tects this and forces the top mosfet off for about 500ns every tenth cycle to allow c b to recharge. the main control loop is shut down by pulling the run/ss pin low. releasing run/ss allows an internal 1.2 m a current source to charge soft-start capacitor c ss . when c ss reaches 1.5v, the main control loop is enabled with the i th voltage clamped at approximately 30% of its maximum value. as c ss continues to charge, the i th pin voltage is gradually released allowing normal, full-current opera- tion. when both run/ss1 and run/ss2 are low, all LTC3707 controller functions are shut down, and the stbymd pin determines if the standby 5v and 3.3v regulators are kept alive. low current operation the fcb pin is a multifunction pin providing two func- tions: 1) an analog input to provide regulation for a secondary winding by temporarily forcing continuous pwm operation on both controllers and 2) a logic input to select between two modes of low current operation. when the fcb pin voltage is below 0.800v, the controller forces continuous pwm current mode operation. in this mode, the top and bottom mosfets are alternately turned on to maintain the output voltage independent of direction of inductor current. when the fcb pin is below v intvcc C 2v but greater than 0.80v, the controller en- ters burst mode operation. burst mode operation sets a minimum output current level before inhibiting the top switch and turns off the synchronous mosfet(s) when the inductor current goes negative. this combination of requirements will, at low currents, force the i th pin below a voltage threshold that will temporarily inhibit turn-on of both output mosfets until the output voltage drops. there is 60mv of hysteresis in the burst comparator b tied to the i th pin. this hysteresis produces output signals to the mosfets that turn them on for several cycles, followed by a variable sleep interval depending upon the load current. the resultant output voltage ripple is held to a very small value by having the hysteretic comparator after the error amplifier gain block. constant frequency operation when the fcb pin is tied to intv cc , burst mode operation is disabled and the forced minimum output current re- quirement is removed. this provides constant frequency, discontinuous (preventing reverse inductor current) cur- rent operation over the widest possible output current range. this constant frequency operation is not as efficient as burst mode operation, but does provide a lower noise, constant frequency operating mode down to approxi- mately 1% of designed maximum output current. voltage should not be applied to the fcb pin prior to the application of voltage to the v in pin. operatio u
11 LTC3707 3707f continuous current (pwm) operation tying the fcb pin to ground will force continuous current operation. this is the least efficient operating mode, but may be desirable in certain applications. the output can source or sink current in this mode. when sinking current while in forced continuous operation, current will be forced back into the main power supply potentially boost- ing the input supply to dangerous voltage levels beware! frequency setting the freqset pin provides frequency adjustment of the internal oscillator from approximately 140khz to 310khz. this input is nominally biased through an internal resistor to the 1.19v reference, setting the oscillator frequency to approximately 220khz. this pin can be driven from an external ac or dc signal source to control the instanta- neous frequency of the oscillator. voltage should not be applied to the freqset pin prior to the application of voltage to the v in pin. intv cc /extv cc power power for the top and bottom mosfet drivers and most other internal circuitry is derived from the intv cc pin. when the extv cc pin is left open, an internal 5v low dropout linear regulator supplies intv cc power. if extv cc is taken above 4.7v, the 5v regulator is turned off and an internal switch is turned on connecting extv cc to intv cc . this allows the intv cc power to be derived from a high efficiency external source such as the output of the regu- lator itself or a secondary winding, as described in the applications information. standby mode pin the stbymd pin is a three-state input that controls common circuitry within the ic as follows: when the stbymd pin is held at ground, both controller run/ss pins are pulled to ground providing a single control pin to shut down both controllers. when the pin is left open, the internal run/ss currents are enabled to charge the run/ss capacitor(s), allowing the turn-on of either con- troller and activating necessary common internal biasing. when the stbymd pin is taken above 2v, both internal linear regulators are turned on independent of the state on the run/ss pins of the two switching regulator control- lers, providing an output power source for wake-up circuitry. decouple the pin with a small capacitor (0.01 m f) to ground if the pin is not connected to a dc potential. output overvoltage protection an overvoltage comparator, ov, guards against transient overshoots (>7.5%) as well as other more serious condi- tions that may overvoltage the output. in this case, the top mosfet is turned off and the bottom mosfet is turned on until the overvoltage condition is cleared. power good (pgood) pin the pgood pin is connected to an open drain of an internal mosfet. the mosfet turns on and pulls the pin low when both the outputs are not within 7.5% of their nominal output levels as determined by their resistive feedback dividers. when both outputs meet the 7.5% require- ment, the mosfet is turned off within 10 m s and the pin is allowed to be pulled up by an external resistor to a source of up to 7v. foldback current, short-circuit detection and short-circuit latchoff the run/ss capacitors are used initially to limit the inrush current of each switching regulator. after the controller has been started and been given adequate time to charge up the output capacitors and provide full load current, the run/ss capacitor is used in a short-circuit time-out circuit. if the output voltage falls to less than 70% of its nominal output voltage, the run/ss capacitor begins discharging on the assumption that the output is in an overcurrent and/or short-circuit condition. if the condition lasts for a long enough period as determined by the size of the run/ss capacitor, the controllers will be shut down until the run/ss pin(s) voltage(s) are recycled. this built- in latchoff can be overridden by providing a >5 m a pull-up at a compliance of 4.2v to the run/ss pin(s). this current shortens the soft start period but also prevents net dis- charge of the run/ss capacitor(s) during an overcurrent and/or short-circuit condition. foldback current limiting is also activated when the output voltage falls below 70% of its nominal level whether or not the short-circuit latchoff (refer to functional diagram) operatio u
12 LTC3707 3707f circuit is enabled. even if a short is present and the short- circuit latchoff is not enabled, a safe, low output current is provided due to internal current foldback and actual power dissipated is low due to the efficient nature of the current mode switching regulator. theory and benefits of 2-phase operation the ltc1628 and the LTC3707 are the first dual high efficiency dc/dc controllers to bring the considerable benefits of 2-phase operation to portable applications. notebook computers, pdas, handheld terminals and au- tomotive electronics will all benefit from the lower input filtering requirement, reduced electromagnetic interfer- ence (emi) and increased efficiency associated with 2-phase operation. why the need for 2-phase operation? up until the ltc1628 was introduced, constant-frequency dual switching regu- lators operated both channels in phase (i.e., single-phase operation). this means that both switches turned on at the same time, causing current pulses of up to twice the amplitude of those for one regulator to be drawn from the input capacitor and battery. these large amplitude current pulses increased the total rms current flowing from the input capacitor, requiring the use of more expensive input capacitors and increasing both emi and losses in the input capacitor and battery. with 2-phase operation, the two channels of the dual- switching regulator are operated 180 degrees out of phase. this effectively interleaves the current pulses drawn by the switches, greatly reducing the overlap time where they add together. the result is a significant reduction in total rms input current, which in turn allows less expen- sive input capacitors to be used, reduces shielding re- quirements for emi and improves real world operating efficiency. figure 3 compares the input waveforms for a representa- tive single-phase dual switching regulator to the LTC3707 2-phase dual switching regulator. an actual measurement of the rms input current under these conditions shows that 2-phase operation dropped the input current from 2.53a rms to 1.55a rms . while this is an impressive reduc- tion in itself, remember that the power losses are propor- tional to i rms 2 , meaning that the actual power wasted is reduced by a factor of 2.66. the reduced input ripple voltage also means less power is lost in the input power path, which could include batteries, switches, trace/con- nector resistances and protection circuitry. improvements in both conducted and radiated emi also directly accrue as a result of the reduced rms input current and voltage. of course, the improvement afforded by 2-phase opera- tion is a function of the dual switching regulators relative duty cycles which, in turn, are dependent upon the input voltage v in (duty cycle = v out /v in ). figure 4 shows how (b) (a) 5v switch 20v/div 3.3v switch 20v/div input current 5a/div input voltage 500mv/div i in(meas) = 1.55a rms 3707 f03b/tiff i in(meas) = 2.53a rms 3707 f03a/tiff figure 3. input waveforms comparing single-phase (a) and 2-phase (b) operation for dual switching regulators converting 12v to 5v and 3.3v at 3a each. the reduced input ripple with the ltc1628 2-phase regulator allows less expensive input capacitors, reduces shielding requirements for emi and improves efficiency (refer to functional diagram) operatio u
13 LTC3707 3707f figure 4. rms input current comparison figure 1 on the first page is a basic LTC3707 application circuit. external component selection is driven by the load requirement, and begins with the selection of r sense and the inductor value. next, the power mosfets and d1 are selected. finally, c in and c out are selected. the circuit shown in figure 1 can be configured for operation up to an input voltage of 28v (limited by the external mosfets). r sense selection for output current r sense is chosen based on the required output current. the LTC3707 current comparator has a maximum thresh- old of 75mv/r sense and an input common mode range of sgnd to 1.1(intv cc ). the current comparator threshold sets the peak of the inductor current, yielding a maximum average output current i max equal to the peak value less half the peak-to-peak ripple current, d i l . allowing a margin for variations in the LTC3707 and external component values yields: r mv i sense max = 50 when using the controller in very low dropout conditions, the maximum output current level will be reduced due to the internal compensation required to meet stability crite- rion for buck regulators operating at greater than 50% duty factor. a curve is provided to estimate this reducton in peak output current level depending upon the operating duty factor. selection of operating frequency the LTC3707 uses a constant frequency architecture with the frequency determined by an internal oscillator capaci- tor. this internal capacitor is charged by a fixed current plus an additional current that is proportional to the voltage applied to the freqset pin. a graph for the voltage applied to the freqset pin vs frequency is given in figure 5. as the operating frequency input voltage (v) 0 input rms current (a) 3.0 2.5 2.0 1.5 1.0 0.5 0 10 20 30 40 3707 f04 single phase dual controller 2-phase dual controller v o1 = 5v/3a v o2 = 3.3v/3a the rms input current varies for single-phase and 2-phase operation for 3.3v and 5v regulators over a wide input voltage range. it can readily be seen that the advantages of 2-phase operation are not just limited to a narrow operating range, but in fact extend over a wide region. a good rule of thumb for most applications is that 2-phase operation will reduce the input capacitor requirement to that for just one channel operating at maximum current and 50% duty cycle. a final question: if 2-phase operation offers such an advantage over single-phase operation for dual switching regulators, why hasnt it been done before? the answer is that, while simple in concept, it is hard to implement. constant-frequency current mode switching regulators require an oscillator derived slope compensation signal to allow stable operation of each regulator at over 50% duty cycle. this signal is relatively easy to derive in single- phase dual switching regulators, but required the develop- ment of a new and proprietary technique to allow 2-phase operation. in addition, isolation between the two channels (refer to functional diagram) operatio u applicatio s i for atio wu uu becomes more critical with 2-phase operation because switch transitions in one channel could potentially disrupt the operation of the other channel. the ltc1628 and the LTC3707 are proof that these hurdles have been surmounted. the new device offers unique advantages for the ever-expanding number of high efficiency power supplies required in portable electronics.
14 LTC3707 3707f is increased the gate charge losses will be higher, reducing efficiency (see efficiency considerations). the maximum switching frequency is approximately 310khz. inductor value calculation the operating frequency and inductor selection are inter- related in that higher operating frequencies allow the use of smaller inductor and capacitor values. so why would anyone ever choose to operate at lower frequencies with larger components? the answer is efficiency. a higher frequency generally results in lower efficiency because of mosfet gate charge losses. in addition to this basic trade-off, the effect of inductor value on ripple current and low current operation must also be considered. the inductor value has a direct effect on ripple current. the inductor ripple current d i l decreases with higher induc- tance or frequency and increases with higher v in : d i fl v v v l out out in = ? ? ? ? 1 1 ()( ) accepting larger values of d i l allows the use of low inductances, but results in higher output voltage ripple and greater core losses. a reasonable starting point for setting ripple current is d i l =0.3(i max ). remember, the maximum d i l occurs at the maximum input voltage. the inductor value also has secondary effects. the transi- tion to burst mode operation begins when the average inductor current required results in a peak current below 25% of the current limit determined by r sense . lower inductor values (higher d i l ) will cause this to occur at lower load currents, which can cause a dip in efficiency in the upper range of low current operation. in burst mode operation, lower inductance values will cause the burst frequency to decrease. inductor core selection once the value for l is known, the type of inductor must be selected. high efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy, or kool m m ? cores. actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. as inductance increases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can con- centrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that induc- tance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! molypermalloy (from magnetics, inc.) is a very good, low loss core material for toroids, but it is more expensive than ferrite. a reasonable compromise from the same manu- facturer is kool m m . toroids are very space efficient, especially when you can use several layers of wire. be- cause they generally lack a bobbin, mounting is more difficult. however, designs for surface mount are available that do not increase the height significantly. power mosfet and d1 selection two external power mosfets must be selected for each controller with the LTC3707: one n-channel mosfet for the top (main) switch, and one n-channel mosfet for the bottom (synchronous) switch. the peak-to-peak drive levels are set by the intv cc voltage. this voltage is typically 5v during start-up (see kool m m is a registered trademark of magnetics, inc. figure 5. freqset pin voltage vs frequency operating frequency (khz) 120 170 220 270 320 freqset pin voltage (v) 3707 f05 2.5 2.0 1.5 1.0 0.5 0 applicatio s i for atio wu uu
15 LTC3707 3707f extv cc pin connection). consequently, logic-level threshold mosfets must be used in most applications. the only exception is if low input voltage is expected (v in < 5v); then, sub-logic level threshold mosfets (v gs(th) < 3v) should be used. pay close attention to the bv dss specification for the mosfets as well; most of the logic level mosfets are limited to 30v or less. selection criteria for the power mosfets include the on resistance r ds(on) , reverse transfer capacitance c rss , input voltage and maximum output current. when the LTC3707 is operating in continuous mode the duty cycles for the top and bottom mosfets are given by: main switch duty cycle v v out in = synchronous switch duty cycle vv v in out in = the mosfet power dissipations at maximum output current are given by: p v v ir kv i c f main out in max ds on in max rss = () + () + ()( )( )() 2 2 1 d () p vv v ir sync in out in max ds on = () + () () 2 1 d where d is the temperature dependency of r ds(on) and k is a constant inversely related to the gate drive current. both mosfets have i 2 r losses while the topside n-channel equation includes an additional term for transition losses, which are highest at high input voltages. for v in < 20v the high current efficiency generally improves with larger mosfets, while for v in > 20v the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c rss actually provides higher efficiency. the synchronous mosfet losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. the term (1+ d ) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve, but d = 0.005/ c can be used as an approximation for low voltage mosfets. c rss is usually specified in the mos- fet characteristics. the constant k = 1.7 can be used to estimate the contributions of the two terms in the main switch dissipation equation. the schottky diode d1 shown in figure 1 conducts during the dead-time between the conduction of the two power mosfets. this prevents the body diode of the bottom mosfet from turning on, storing charge during the dead- time and requiring a reverse recovery period that could cost as much as 3% in efficiency at high v in . a 1a to 3a schottky is generally a good compromise for both regions of operation due to the relatively small average current. larger diodes result in additional transition losses due to their larger junction capacitance. c in and c out selection the selection of c in is simplified by the multiphase archi- tecture and its impact on the worst-case rms current drawn through the input network (battery/fuse/capacitor). it can be shown that the worst case rms current occurs when only one controller is operating. the controller with the highest (v out )(i out ) product needs to be used in the formula below to determine the maximum rms current requirement. increasing the output current, drawn from the other out-of-phase controller, will actually decrease the input rms ripple current from this maximum value (see figure 4). the out-of-phase technique typically re- duces the input capacitors rms ripple current by a factor of 30% to 70% when compared to a single phase power supply solution. the type of input capacitor, value and esr rating have efficiency effects that need to be considered in the selec- tion process. the capacitance value chosen should be sufficient to store adequate charge to keep high peak battery currents down. 20 m f to 40 m f is usually sufficient for a 25w output supply operating at 200khz. the esr of the capacitor is important for capacitor power dissipation as well as overall battery efficiency. all of the power (rms ripple current ? esr) not only heats up the capacitor but wastes power from the battery. applicatio s i for atio wu uu
16 LTC3707 3707f medium voltage (20v to 35v) ceramic, tantalum, os-con and switcher-rated electrolytic capacitors can be used as input capacitors, but each has drawbacks: ceramic voltage coefficients are very high and may have audible piezoelec- tric effects; tantalums need to be surge-rated; os-cons suffer from higher inductance, larger case size and limited surface-mount applicability; electrolytics higher esr and dryout possibility require several to be used. multiphase systems allow the lowest amount of capacitance overall. as little as one 22 m f or two to three 10 m f ceramic capaci- tors are an ideal choice in a 20w to 50w power supply due to their extremely low esr. even though the capacitance at 20v is substantially below their rating at zero-bias, very low esr loss makes ceramics an ideal candidate for highest efficiency battery operated systems. also con- sider parallel ceramic and high quality electrolytic capaci- tors as an effective means of achieving esr and bulk capacitance goals. in continuous mode, the source current of the top n-chan- nel mosfet is a square wave of duty cycle v out /v in . to prevent large voltage transients, a low esr input capacitor sized for the maximum rms current of one channel must be used. the maximum rms capacitor current is given by: c quiredi i vvv v in rms max out in out in re / ? - () [] 12 this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst case condition is com- monly used for design because even significant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. always consult the manufacturer if there is any question. the benefit of the LTC3707 multiphase can be calculated by using the equation above for the higher power control- ler and then calculating the loss that would have resulted if both controller channels switch on at the same time. the total rms power lost is lower when both controllers are operating due to the interleaving of current pulses through the input capacitors esr. this is why the input capacitors requirement calculated above for the worst-case control- ler is adequate for the dual controller design. remember that input protection fuse resistance, battery resistance and pc board trace resistance losses are also reduced due to the reduced peak currents in a multiphase system. the overall benefit of a multiphase design will only be fully realized when the source impedance of the power supply/ battery is included in the efficiency testing. the drains of the two top mosfets should be placed within 1cm of each other and share a common c in (s). separating the drains and c in may produce undesirable voltage and current resonances at v in . the selection of c out is driven by the required effective series resistance (esr). typically once the esr require- ment is satisfied the capacitance is adequate for filtering. the output ripple ( d v out ) is determined by: dd v i esr fc out l out ?+ ? ? ? ? 1 8 where f = operating frequency, c out = output capacitance, and d i l = ripple current in the inductor. the output ripple is highest at maximum input voltage since d i l increases with input voltage. with d i l = 0.3i out(max) the output ripple will typically be less than 50mv at max v in assum- ing: c out recommended esr < 2 r sense and c out > 1/(8fr sense ) the first condition relates to the ripple current into the esr of the output capacitance while the second term guaran- tees that the output capacitance does not significantly discharge during the operating frequency period due to ripple current. the choice of using smaller output capaci- tance increases the ripple voltage due to the discharging term but can be compensated for by using capacitors of very low esr to maintain the ripple voltage at or below 50mv. the i th pin opti-loop compensation compo- nents can be optimized to provide stable, high perfor- mance transient response regardless of the output capaci- tors selected. applicatio s i for atio wu uu
17 LTC3707 3707f manufacturers such as nichicon, united chemicon and sanyo can be considered for high performance through- hole capacitors. the os-con semiconductor dielectric capacitor available from sanyo has the lowest (esr)(size) product of any aluminum electrolytic at a somewhat higher price. an additional ceramic capacitor in parallel with os-con capacitors is recommended to reduce the inductance effects. in surface mount applications multiple capacitors may need to be used in parallel to meet the esr, rms current handling and load step requirements of the application. aluminum electrolytic, dry tantalum and special polymer capacitors are available in surface mount packages. spe- cial polymer surface mount capacitors offer very low esr but have lower storage capacity per unit volume than other capacitor types. these capacitors offer a very cost-effec- tive output capacitor solution and are an ideal choice when combined with a controller having high loop bandwidth. tantalum capacitors offer the highest capacitance density and are often used as output capacitors for switching regulators having controlled soft-start. several excellent surge-tested choices are the avx tps, avx tpsv or the kemet t510 series of surface mount tantalums, available in case heights ranging from 2mm to 4mm. aluminum electrolytic capacitors can be used in cost-driven applica- tions providing that consideration is given to ripple current ratings, temperature and long term reliability. a typical application will require several to many aluminum electro- lytic capacitors in parallel. a combination of the above mentioned capacitors will often result in maximizing per- formance and minimizing overall cost. other capacitor types include nichicon pl series, nec neocap, pansonic sp and sprague 595d series. consult manufacturers for other specific recommendations. intv cc regulator an internal p-channel low dropout regulator produces 5v at the intv cc pin from the v in supply pin. intv cc powers the drivers and internal circuitry within the LTC3707. the intv cc pin regulator can supply a peak current of 40ma and must be bypassed to ground with a minimum of 4.7 m f tantalum, 10 m f special polymer, or low esr type electrolytic capacitor. a 1 m f ceramic capacitor placed directly adjacent to the intv cc and pgnd ic pins is highly recommended. good bypassing is necessary to supply the high transient currents required by the mosfet gate drivers and to prevent interaction between channels. higher input voltage applications in which large mosfets are being driven at high frequencies may cause the maxi- mum junction temperature rating for the LTC3707 to be exceeded. the system supply current is normally domi- nated by the gate charge current. additional external loading of the intv cc and 3.3v linear regulators also needs to be taken into account for the power dissipation calculations. the total intv cc current can be supplied by either the 5v internal linear regulator or by the extv cc input pin. when the voltage applied to the extv cc pin is less than 4.7v, all of the intv cc current is supplied by the internal 5v linear regulator. power dissipation for the ic in this case is highest: (v in )(i intvcc ), and overall efficiency is lowered. the gate charge current is dependent on operating frequency as discussed in the efficiency consid- erations section. the junction temperature can be esti- mated by using the equations given in note 2 of the electrical characteristics. for example, the LTC3707 v in current is limited to less than 24ma from a 24v supply when not using the extv cc pin as follows: t j = 70 c + (24ma)(24v)(95 c/w) = 125 c use of the extv cc input pin reduces the junction tempera- ture to: t j = 70 c + (24ma)(5v)(95 c/w) = 81 c dissipation should be calculated to also include any added current drawn from the internal 3.3v linear regulator. to prevent maximum junction temperature from being ex- ceeded, the input supply current must be checked operat- ing in continuous mode at maximum v in . extv cc connection the LTC3707 contains an internal p-channel mosfet switch connected between the extv cc and intv cc pins. when the voltage applied to extv cc rises above 4.7v, the internal regulator is turned off and the switch closes, connecting the extv cc pin to the intv cc pin thereby supplying internal power. the switch remains closed as long as the voltage applied to extv cc remains above 4.5v. this allows the mosfet driver and control power to be applicatio s i for atio wu uu
18 LTC3707 3707f derived from the output during normal operation (4.7v < v out < 7v) and from the internal regulator when the output is out of regulation (start-up, short-circuit). if more cur- rent is required through the extv cc switch than is speci- fied, an external schottky diode can be added between the extv cc and intv cc pins. do not apply greater than 7v to the extv cc pin and ensure that extv cc < v in . significant efficiency gains can be realized by powering intv cc from the output, since the v in current resulting from the driver and control currents will be scaled by a factor of (duty cycle)/(efficiency). for 5v regulators this supply means connecting the extv cc pin directly to v out . however, for 3.3v and other lower voltage regulators, additional circuitry is required to derive intv cc power from the output. the following list summarizes the four possible connec- tions for extv cc: 1. extv cc left open (or grounded). this will cause intv cc to be powered from the internal 5v regulator resulting in an efficiency penalty of up to 10% at high input voltages. 2. extv cc connected directly to v out . this is the normal connection for a 5v regulator and provides the highest efficiency. 3. extv cc connected to an external supply. if an external supply is available in the 5v to 7v range, it may be used to power extv cc providing it is compatible with the mosfet gate drive requirements. figure 6a. secondary output loop & extv cc connection figure 6b. capacitive charge pump for extv cc 4. extv cc connected to an output-derived boost net- work. for 3.3v and other low voltage regulators, efficiency gains can still be realized by connecting extv cc to an output-derived voltage that has been boosted to greater than 4.7v. this can be done with either the inductive boost winding as shown in figure 6a or the capacitive charge pump shown in figure 6b. the charge pump has the advantage of simple magnetics. topside mosfet driver supply (c b , d b ) external bootstrap capacitors c b connected to the boost pins supply the gate drive voltages for the topside mosfets. capacitor c b in the functional diagram is charged though external diode d b from intv cc when the sw pin is low. when one of the topside mosfets is to be turned on, the driver places the c b voltage across the gate-source of the desired mosfet. this enhances the mosfet and turns on the topside switch. the switch node voltage, sw, rises to v in and the boost pin follows. with the topside mosfet on, the boost voltage is above the input supply: v boost = v in + v intvcc . the value of the boost capacitor c b needs to be 100 times that of the total input capacitance of the topside mosfet(s). the reverse breakdown of the exter- nal schottky diode must be greater than v in(max) . when adjusting the gate drive level, the final arbiter is the total input current for the regulator. if a change is made and the input current decreases, then the efficiency has improved. if there is no change in input current, then there is no change in efficiency. extv cc fcb sgnd v in tg1 sw bg1 pgnd LTC3707 r sense v out v sec + c out + 1 f 3707 f06a n-ch n-ch r6 + c in v in t1 1:n optional extv cc connection 5v < v sec < 7v r5 extv cc v in tg1 sw bg1 pgnd LTC3707 v out vn2222ll + c out 3707 f06b n-ch n-ch + c in + 1 f v in l1 bat85 bat85 bat85 0.22 f r sense applicatio s i for atio wu uu
19 LTC3707 3707f output voltage the LTC3707 output voltages are each set by an external feedback resistive divider carefully placed across the output capacitor. the resultant feedback signal is com- pared with the internal precision 0.800v voltage reference by the error amplifier. the output voltage is given by the equation: vv r r out =+ ? ? ? ? 08 1 2 1 . sense + /sense C pins the common mode input range of the current comparator sense pins is from 0v to (1.1)intv cc . continuous linear operation is guaranteed throughout this range allowing output voltage setting from 0.8v to 7.7v, depending upon the voltage applied to extv cc . a differential npn input stage is biased with internal resistors from an internal 2.4v source as shown in the functional diagram. this requires that current either be sourced or sunk from the sense pins depending on the output voltage. if the output voltage is below 2.4v current will flow out of both sense pins to the main output. the output can be easily preloaded by the v out resistive divider to compensate for the current comparators negative input bias current. the maximum current flowing out of each pair of sense pins is: i sense + + i sense C = (2.4v C v out )/24k since v osense is servoed to the 0.8v reference voltage, we can choose r1 in figure 2 to have a maximum value to absorb this current. rk v vv max out 124 08 24 () . . = ? ? ? ? for v out < 2.4v regulating an output voltage of 1.8v, the maximum value of r1 should be 32k. note that for an output voltage above 2.4v, r1 has no maximum value necessary to absorb the sense currents; however, r1 is still bounded by the v osense feedback current. soft-start/run function the run/ss1 and run/ss2 pins are multipurpose pins that provide a soft-start function and a means to shut down the LTC3707. soft-start reduces the input power sources surge currents by gradually increasing the controllers current limit (proportional to v ith ). this pin can also be used for power supply sequencing. an internal 1.2 m a current source charges up the c ss capacitor . when the voltage on run/ss1 (run/ss2) reaches 1.5v, the particular controller is permitted to start operating. as the voltage on run/ss increases from 1.5v to 3.0v, the internal current limit is increased from 25mv/ r sense to 75mv/r sense . the output current limit ramps up slowly, taking an additional 1.25s/ m f to reach full current. the output current thus ramps up slowly, reduc- ing the starting surge current required from the input power supply. if run/ss has been pulled all the way to ground there is a delay before starting of approximately: t v a csfc delay ss ss = m =m () 15 12 125 . . ./ t vv a csfc iramp ss ss = - m =m () 315 12 125 . . ./ by pulling both run/ss pins below 1v and/or pulling the stbymd pin below 0.2v, the LTC3707 is put into low current shutdown (i q = 20 m a). the run/ss pins can be driven directly from logic as shown in figure 7. diode d1 in figure 7 reduces the start delay but allows c ss to ramp up slowly providing the soft-start function. each run/ss pin has an internal 6v zener clamp (see functional diagram). figure 7. run/ss pin interfacing applicatio s i for atio wu uu 3.3v or 5v run/ss v in intv cc run/ss d1 c ss r ss * c ss r ss * 3707 f07 *optional to defeat overcurrent latchoff (a) (b)
20 LTC3707 3707f fault conditions: overcurrent latchoff the run/ss pins also provide the ability to latch off the controller(s) when an overcurrent condition is detected. the run/ss capacitor, c ss , is used initially to turn on and limit the inrush current. after the controller has been started and been given adequate time to charge up the output capacitor and provide full load current, the run/ss capacitor is used for a short-circuit timer. if the regulators output voltage falls to less than 70% of its nominal value after c ss reaches 4.2v, c ss begins discharging on the assumption that the output is in an overcurrent condition. if the condition lasts for a long enough period as deter- mined by the size of the c ss and the specified discharge current, the controller will be shut down until the run/ss pin voltage is recycled. if the overload occurs during start- up, the time can be approximated by: t lo1 ? [c ss (4.1 C 1.5 + 4.1 C 3.5)]/(1.2 m a) = 2.7 ? 10 6 (c ss ) if the overload occurs after start-up the voltage on c ss will begin discharging from the zener clamp voltage: t lo2 ? [c ss (6 C 3.5)]/(1.2 m a) = 2.1 ? 10 6 (c ss ) this built-in overcurrent latchoff can be overridden by providing a pull-up resistor to the run/ss pin as shown in figure 7. this resistance shortens the soft-start period and prevents the discharge of the run/ss capacitor during an over current condition. tying this pull-up resis- tor to v in as in figure 7a, defeats overcurrent latchoff. diode-connecting this pull-up resistor to intv cc , as in figure 7b, eliminates any extra supply current during controller shutdown while eliminating the intv cc loading from preventing controller start-up. why should you defeat overcurrent latchoff? during the prototyping stage of a design, there may be a problem with noise pickup or poor layout causing the protection circuit to latch off. defeating this feature will easily allow troubleshooting of the circuit and pc layout. the internal short-circuit and foldback current limiting still remains active, thereby protecting the power supply system from failure. after the design is complete, a decision can be made whether to enable the latchoff feature. the value of the soft-start capacitor c ss may need to be scaled with output voltage, output capacitance and load current characteristics. the minimum soft-start capaci- tance is given by: c ss > (c out )(v out ) (10 C4 ) (r sense ) the minimum recommended soft-start capacitor of c ss = 0.1 m f will be sufficient for most applications. fault conditions: current limit and current foldback the LTC3707 current comparator has a maximum sense voltage of 75mv resulting in a maximum mosfet current of 75mv/r sense . the maximum value of current limit generally occurs with the largest v in at the highest ambi- ent temperature, conditions that cause the highest power dissipation in the top mosfet. the LTC3707 includes current foldback to help further limit load current when the output is shorted to ground. the foldback circuit is active even when the overload shutdown latch described above is overridden. if the output falls below 70% of its nominal output level, then the maximum sense voltage is progressively lowered from 75mv to 25mv. under short-circuit conditions with very low duty cycles, the LTC3707 will begin cycle skipping in order to limit the short-circuit current. in this situation the bottom mosfet will be dissipating most of the power but less than in normal operation. the short-circuit ripple current is determined by the minimum on-time t on(min) of the LTC3707 (less than 200ns), the input voltage and inductor value: d i l(sc) = t on(min) (v in /l) the resulting short-circuit current is: i mv r i sc sense lsc =+ 25 1 2 d () applicatio s i for atio wu uu
21 LTC3707 3707f fault conditions: overvoltage protection (crowbar) the overvoltage crowbar is designed to blow a system input fuse when the output voltage of the regulator rises much higher than nominal levels. the crowbar causes huge currents to flow, that blow the fuse to protect against a shorted top mosfet if the short occurs while the controller is operating. a comparator monitors the output for overvoltage condi- tions. the comparator (ov) detects overvoltage faults greater than 7.5% above the nominal output voltage. when this condition is sensed, the top mosfet is turned off and the bottom mosfet is turned on until the overvolt- age condition is cleared. the output of this comparator is only latched by the overvoltage condition itself and will therefore allow a switching regulator system having a poor pc layout to function while the design is being debugged. the bottom mosfet remains on continuously for as long as the ov condition persists; if v out returns to a safe level, normal operation automatically resumes. a shorted top mosfet will result in a high current condition which will open the system fuse. the switching regulator will regu- late properly with a leaky top mosfet by altering the duty cycle to accommodate the leakage. the standby mode (stbymd) pin function the standby mode (stbymd) pin provides several choices for start-up and standby operational modes. if the pin is pulled to ground, the run/ss pins for both controllers are internally pulled to ground, preventing start-up and thereby providing a single control pin for turning off both control- lers at once. if the pin is left open or decoupled with a capacitor to ground, the run/ss pins are each internally provided with a starting current enabling external control for turning on each controller independently. if the pin is provided with a current of >3 m a at a voltage greater than 2v, both internal linear regulators (intv cc and 3.3v) will be on even when both controllers are shut down. in this mode, the onboard 3.3v and 5v linear regulators can provide power to keep-alive functions such as a keyboard controller. this pin can also be used as a latching on and/ or latching off power switch if so designed. frequency of operation the LTC3707 has an internal voltage controlled oscillator. the frequency of this oscillator can be varied over a 2 to 1 range. the pin is internally self-biased at 1.19v, resulting in a free-running frequency of approximately 220khz. the freqset pin can be grounded to lower this frequency to approximately 140khz or tied to the intv cc pin to yield approximately 310khz. the freqset pin may be driven with a voltage from 0 to intv cc to fix or modulate the oscillator frequency as shown in figure 5. minimum on-time considerations minimum on-time t on(min) is the smallest time duration that the LTC3707 is capable of turning on the top mosfet. it is determined by internal timing delays and the gate charge required to turn on the top mosfet. low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that t v vf on min out in () () < if the duty cycle falls below what can be accommodated by the minimum on-time, the LTC3707 will begin to skip cycles. the output voltage will continue to be regulated, but the ripple voltage and current will increase. the minimum on-time for the LTC3707 is generally less than 200ns. however, as the peak sense voltage decreases the minimum on-time gradually increases up to about 300ns. this is of particular concern in forced continuous applications with low ripple current at light loads. if the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple. applicatio s i for atio wu uu
22 LTC3707 3707f fcb pin operation the fcb pin can be used to regulate a secondary winding or as a logic level input. continuous operation is forced when the fcb pin drops below 0.8v. during continuous mode, current flows continuously in the transformer pri- mary. the secondary winding(s) draw current only when the bottom, synchronous switch is on. when primary load currents are low and/or the v in /v out ratio is low, the synchronous switch may not be on for a sufficient amount of time to transfer power from the output capacitor to the secondary load. forced continuous operation will support secondary windings providing there is sufficient synchro- nous switch duty factor. thus, the fcb input pin removes the requirement that power must be drawn from the inductor primary in order to extract power from the auxiliary windings. with the loop in continuous mode, the auxiliary outputs may nominally be loaded without regard to the primary output load. the secondary output voltage v sec is normally set as shown in figure 6a by the turns ratio n of the transformer: v sec @ (n + 1) v out however, if the controller goes into burst mode operation and halts switching due to a light primary load current, then v sec will droop. an external resistive divider from v sec to the fcb pin sets a minimum voltage v sec(min) : vv r r sec min () . ?+ ? ? ? ? 08 1 6 5 if v sec drops below this level, the fcb voltage forces temporary continuous switching operation until v sec is again above its minimum. in order to prevent erratic operation if no external connec- tions are made to the fcb pin, the fcb pin has a 0.18 m a internal current source pulling the pin high. include this current when choosing resistor values r5 and r6. the following table summarizes the possible states avail- able on the fcb pin: table 1 fcb pin condition 0v to 0.75v forced continuous (current reversal allowedburst inhibited) 0.85v < v fcb < v intvcc C 2v minimum peak current induces burst mode operation no current reversal allowed feedback resistors regulating a secondary winding = v intvcc burst mode operation disabled constant frequency mode enabled no current reversal allowed no minimum peak current voltage positioning voltage positioning can be used to minimize peak-to-peak output voltage excursions under worst-case transient loading conditions. the open-loop dc gain of the control loop is reduced depending upon the maximum load step specifications. voltage positioning can easily be added to the LTC3707 by loading the i th pin with a resistive divider having a thevenin equivalent voltage source equal to the midpoint operating voltage of the error amplifier, or 1.2v (see figure 8). the resistive load reduces the dc loop gain while main- taining the linear control range of the error amplifier. the maximum output voltage deviation can theoretically be reduced to half or alternatively the amount of output capacitance can be reduced for a particular application. a complete explanation is included in design solutions 10. (see www.linear-tech.com) i th r c r t1 intv cc c c 3707 f08 LTC3707 r t2 figure 8. active voltage positioning applied to the LTC3707 applicatio s i for atio wu uu
23 LTC3707 3707f 3. i 2 r losses are predicted from the dc resistances of the fuse (if used), mosfet, inductor, current sense resistor, and input and output capacitor esr. in continuous mode the average output current flows through l and r sense , but is chopped between the topside mosfet and the synchronous mosfet. if the two mosfets have approxi- mately the same r ds(on) , then the resistance of one mosfet can simply be summed with the resistances of l, r sense and esr to obtain i 2 r losses. for example, if each r ds(on) = 30m w , r l = 50m w , r sense = 10m w and r esr = 40m w (sum of both input and output capacitance losses), then the total resistance is 130m w . this results in losses ranging from 3% to 13% as the output current increases from 1a to 5a for a 5v output, or a 4% to 20% loss for a 3.3v output. efficiency varies as the inverse square of v out for the same external components and output power level. the combined effects of increasingly lower output voltages and higher currents required by high performance digital systems is not doubling but quadrupling the importance of loss terms in the switching regulator system! 4. transition losses apply only to the topside mosfet(s), and become significant only when operating at high input voltages (typically 15v or greater). transition losses can be estimated from: transition loss = (1.7) v in 2 i o(max) c rss f other hidden losses such as copper trace and internal battery resistances can account for an additional 5% to 10% efficiency degradation in portable systems. it is very important to include these system level losses during the design phase. the internal battery and fuse resistance losses can be minimized by making sure that c in has adequate charge storage and very low esr at the switch- ing frequency. a 25w supply will typically require a minimum of 20 m f to 40 m f of capacitance having a maxi- mum of 20m w to 50m w of esr. the LTC3707 2-phase architecture typically halves this input capacitance re- quirement over competing solutions. other losses includ- ing schottky conduction losses during dead-time and inductor core losses generally account for less than 2% total additional loss. efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. percent efficiency can be expressed as: %efficiency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percentage of input power. although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in LTC3707 circuits: 1) LTC3707 v in current (in- cluding loading on the 3.3v internal regulator), 2) intv cc regulator current, 3) i 2 r losses, 4) topside mosfet transition losses. 1. the v in current has two components: the first is the dc supply current given in the electrical characteristics table, which excludes mosfet driver and control currents; the second is the current drawn from the 3.3v linear regulator output. v in current typically results in a small (<0.1%) loss. 2. intv cc current is the sum of the mosfet driver and control currents. the mosfet driver current results from switching the gate capacitance of the power mosfets. each time a mosfet gate is switched from low to high to low again, a packet of charge dq moves from intv cc to ground. the resulting dq/dt is a current out of intv cc that is typically much larger than the control circuit current. in continuous mode, i gatechg =f(q t +q b ), where q t and q b are the gate charges of the topside and bottom side mosfets. supplying intv cc power through the extv cc switch input from an output-derived source will scale the v in current required for the driver and control circuits by a factor of (duty cycle)/(efficiency). for example, in a 20v to 5v application, 10ma of intv cc current results in approxi- mately 2.5ma of v in current. this reduces the mid-current loss from 10% or more (if the driver was powered directly from v in ) to only a few percent. applicatio s i for atio wu uu
24 LTC3707 3707f checking transient response the regulator loop response can be checked by looking at the load current transient response. switching regulators take several cycles to respond to a step in dc (resistive) load current. when a load step occurs, v out shifts by an amount equal to d i load (esr), where esr is the effective series resistance of c out . d i load also begins to charge or discharge c out generating the feedback error signal that forces the regulator to adapt to the current change and return v out to its steady-state value. during this recovery time v out can be monitored for excessive overshoot or ringing, which would indicate a stability problem. opti- loop compensation allows the transient response to be optimized over a wide range of output capacitance and esr values. the availability of the i th pin not only allows optimization of control loop behavior but also provides a dc coupled and ac filtered closed loop response test point. the dc step, rise time and settling at this test point truly reflects the closed loop response . assuming a pre- dominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. the bandwidth can also be estimated by examining the rise time at the pin. the i th external components shown in the figure 1 circuit will provide an adequate starting point for most applications. the i th series r c -c c filter sets the dominant pole-zero loop compensation. the values can be modified slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the final pc layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be selected because the various types and values determine the loop gain and phase. an output current pulse of 20% to 80% of full-load current having a rise time of 1 m s to 10 m s will produce output voltage and i th pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. placing a power mosfet directly across the output capacitor and driving the gate with an appropriate signal generator is a practical way to produce a realistic load step condition. the initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. this is why it is better to look at the i th pin signal which is in the feedback loop and is the filtered and compensated control loop response. the gain of the loop will be increased by increasing r c and the bandwidth of the loop will be increased by decreasing c c . if r c is increased by the same factor that c c is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. a second, more severe transient is caused by switching in loads with large (>1 m f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. if the ratio of c load to c out is greater than1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 ? c load . thus a 10 m f capacitor would require a 250 m s rise time, limiting the charging current to about 200ma. applicatio s i for atio wu uu
25 LTC3707 3707f automotive considerations: plugging into the cigarette lighter as battery-powered devices go mobile, there is a natural interest in plugging into the cigarette lighter in order to conserve or even recharge battery packs during operation. but before you connect, be advised: you are plugging into the supply from hell. the main power line in an automobile is the source of a number of nasty potential transients, including load-dump, reverse-battery, and double-bat- tery. load-dump is the result of a loose battery cable. when the cable breaks connection, the field collapse in the alternator can cause a positive spike as high as 60v which takes several hundred milliseconds to decay. reverse-battery is figure 9. automotive application protection just what it says, while double-battery is a consequence of tow-truck operators finding that a 24v jump start cranks cold engines faster than 12v. the network shown in figure 9 is the most straight forward approach to protect a dc/dc converter from the ravages of an automotive power line. the series diode prevents current from flowing during reverse-battery, while the transient suppressor clamps the input voltage during load-dump. note that the transient suppressor should not conduct during double-battery operation, but must still clamp the input voltage below breakdown of the converter. although the LTC3707 has a maximum input voltage of 30v, most applications will be limited to 28v by the mosfet bvdss. v in 3707 f09 LTC3707 transient voltage suppressor general instrument 1.5ka24a 50a i pk rating 12v applicatio s i for atio wu uu
26 LTC3707 3707f design example as a design example for one channel, assume v in = 12v(nominal), v in = 22v(max), v out = 1.8v, i max = 5a, and f = 300khz. the inductance value is chosen first based on a 30% ripple current assumption. the highest value of ripple current occurs at the maximum input voltage. tie the freqset pin to the intv cc pin for 300khz operation. the minimum inductance for 30% ripple current is: d i v fl v v l out out in = ? ? ? ? ()( ) 1 a 4.7 m h inductor will produce 23% ripple current and a 3.3 m h will result in 33%. the peak inductor current will be the maximum dc value plus one half the ripple current, or 5.84a, for the 3.3 m h value. increasing the ripple current will also help ensure that the minimum on-time of 200ns is not violated. the minimum on-time occurs at maximum v in : t v vf v v khz ns on min out in max () () . () == = 18 22 300 273 the r sense resistor value can be calculated by using the maximum current sense voltage specification with some accommodation for tolerances: r mv a sense ?w 60 584 001 . . since the output voltage is below 2.4v the output resistive divider will need to be sized to not only set the output voltage but also to absorb the sense pins specified input current. rk v vv k v vv k max out 124 08 24 24 08 24 18 32 () . . . .. = ? ? ? ? = ? ? ? ? = choosing 1% resistors; r1 = 25.5k and r2 = 32.4k yields an output voltage of 1.816v. the power dissipation on the top side mosfet can be easily estimated. choosing a siliconix si4412dy results in; r ds(on) = 0.042 w , c rss = 100pf. at maximum input voltage with t(estimated) = 50 c: p v v cc v a pf khz mw main = () + [] w () + ()()( )( ) = 18 22 5 1 0 005 50 25 0 042 1 7 22 5 100 300 220 2 2 . (. )( ) .. a short-circuit to ground will result in a folded back current of: i mv ns v h a sc = w + m ? ? ? ? = 25 001 1 2 200 22 33 32 . () . . with a typical value of r ds(on) and d = (0.005/ c)(20) = 0.1. the resulting power dissipated in the bottom mosfet is: p vv v a mw sync = ()() w () = 22 1 8 22 32 11 0042 434 2 . ... which is less than under full-load conditions. c in is chosen for an rms current rating of at least 3a at temperature assuming only this channel is on. c out is chosen with an esr of 0.02 w for low output ripple. the output ripple in continuous mode will be highest at the maximum input voltage. the output voltage ripple due to esr is approximately: v oripple = r esr( d il) = 0.02 w (1.67a) = 33mv pCp applicatio s i for atio wu uu
27 LTC3707 3707f pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3707. these items are also illustrated graphically in the layout diagram of figure 10. the figure 11 illustrates the current waveforms present in the various branches of the 2-phase synchronous regulators operating in the continuous mode. check the following in your layout: 1. are the top n-channel mosfets m1 and m3 located within 1cm of each other with a common drain connection at c in ? do not attempt to split the input decoupling for the two channels as it can cause a large resonant loop. 2. are the signal and power grounds kept separate? the combined LTC3707 signal ground pin and the ground return of c intvcc must return to the combined c out (C) terminals. the path formed by the top n-channel mosfet, schottky diode and the c in capacitor should have short leads and pc trace lengths. the output capacitor (C) terminals should be connected as close as possible to the (C) terminals of the input capacitor by placing the capaci- tors next to each other and away from the schottky loop described above. 3. do the LTC3707 v osense pins resistive dividers con- nect to the (+) terminals of c out ? the resistive divider must be connected between the (+) terminal of c out and figure 10. LTC3707 recommended printed circuit layout diagram c b2 c b1 r pu pgood v pull-up (<7v) c intvcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 + c in d1 m1 m2 m3 m4 d2 + c vin v in r in intv cc 3.3v r4 r3 r2 r1 run/ss1 sense1 + sense1 v osense1 freqset stbymd fcb i th1 sgnd 3.3v out i th2 v osense2 sense2 sense2 + pgood tg1 sw1 boost1 v in bg1 extv cc intv cc pgnd bg2 boost2 sw2 tg2 run/ss2 LTC3707 l1 l2 c out1 v out1 gnd v out2 3707 f10 + c out2 + r sense r sense applicatio s i for atio wu uu
28 LTC3707 3707f figure 11. branch current waveforms applicatio s i for atio wu u u signal ground and a small v osense decoupling capacitor should be as close as possible to the LTC3707 sgnd pin. the r2 and r4 connections should not be along the high current input feeds from the input capacitor(s). 4. are the sense C and sense + leads routed together with minimum pc trace spacing? the filter capacitor between sense + and sense C should be as close as possible to the ic. ensure accurate current sensing with kelvin connections at the sense resistor. 5. is the intv cc decoupling capacitor connected close to the ic, between the intv cc and the power ground pins? this capacitor carries the mosfet drivers current peaks. an additional 1 m f ceramic capacitor placed immediately next to the intv cc and pgnd pins can help improve noise performance substantially. 6. keep the switching nodes (sw1, sw2), top gate nodes (tg1, tg2), and boost nodes (boost1, boost2) away from sensitive small-signal nodes, especially from the opposites channels voltage and current sensing feedback pins. all of these nodes have very large and fast moving signals and therefore should be kept on the output side of the LTC3707 and occupy minimum pc trace area. r l1 d1 l1 sw1 r sense1 v out1 c out1 + v in c in r in + r l2 d2 bold lines indicate high, switching current lines. keep lines to a minimum length. l2 sw2 3707 f11 r sense2 v out2 c out2 +
29 LTC3707 3707f applicatio s i for atio wu u u 7. use a modified star ground technique: a low imped- ance, large copper area central grounding point on the same side of the pc board as the input and output capacitors with tie-ins for the bottom of the intv cc decoupling capacitor, the bottom of the voltage feedback resistive divider and the sgnd pin of the ic. pc board layout debugging start with one controller on at a time. it is helpful to use a dc-50mhz current probe to monitor the current in the inductor while testing the circuit. monitor the output switching node (sw pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage as well. check for proper performance over the operating voltage and current range expected in the appli- cation. the frequency of operation should be maintained over the input voltage range down to dropout and until the output load drops below the low current operation thresh- oldtypically 10% to 20% of the maximum designed current level in burst mode operation. the duty cycle percentage should be maintained from cycle to cycle in a well-designed, low noise pcb imple- mentation. variation in the duty cycle at a subharmonic rate can suggest noise pickup at the current or voltage sensing inputs or inadequate loop compensation. over- compensation of the loop can be used to tame a poor pc layout if regulator bandwidth optimization is not required. only after each controller is checked for their individual performance should both controllers be turned on at the same time. a particularly difficult region of operation is when one controller channel is nearing its current com- parator trip point when the other channel is turning on its top mosfet. this occurs around 50% duty cycle on either channel due to the phasing of the internal clocks and may cause minor duty cycle jitter. short-circuit testing can be performed to verify proper overcurrent latchoff, or 5 m a can be provided to the run/ ss pin(s) by resistors from v in to prevent the short-circuit latchoff from occurring. reduce v in from its nominal level to verify operation of the regulator in dropout. check the operation of the undervoltage lockout circuit by further lowering v in while monitoring the outputs to verify operation. investigate whether any problems exist only at higher output currents or only at higher input voltages. if prob- lems coincide with high input voltages and low output currents, look for capacitive coupling between the boost, sw, tg, and possibly bg connections and the sensitive voltage and current pins. the capacitor placed across the current sensing pins needs to be placed immediately adjacent to the pins of the ic. this capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. if problems are en- countered with high current output loading at lower input voltages, look for inductive coupling between c in , schottky and the top mosfet components to the sensitive current and voltage sensing traces. in addition, investigate com- mon ground path voltage pickup between these compo- nents and the sgnd pin of the ic. an embarrassing problem, which can be missed in an otherwise properly working switching regulator, results when the current sensing leads are hooked up backwards. the output voltage under this improper hookup will still be maintained but the advantages of current mode control will not be realized. compensation of the voltage loop will be much more sensitive to component selection. this behavior can be investigated by temporarily shorting out the current sensing resistordont worry, the regulator will still maintain control of the output voltage.
30 LTC3707 3707f figure 12. LTC3707 high efficiency low noise 5v/3a, 3.3v/5a, 12/120ma regulator 0.1 f 0.1 f 4.7 f 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 + 22 f 50v d1 mbrm 140t3 mbrs1100t3 d2 mbrm 140t3 m1 m2 m3 m4 1 f 10v cmdsh-3tr cmdsh-3tr 0.1 f 10 0.01 0.015 intv cc 3.3v 0.1 f 20k 1% 105k, 1% 33pf 15k 33pf 15k 1000pf 1000pf 1000pf 1000pf 0.1 f 20k 1% 63.4k 1% run/ss1 sense1 + sense1 v osense1 freqset stbymd fcb i th1 sgnd 3.3v out i th2 v osense2 sense2 sense2 + pgood tg1 sw1 boost1 v in bg1 extv cc intv cc pgnd bg2 boost2 sw2 tg2 run/ss2 LTC3707 t1, 1:1.8 10 h l1 6.3 h 150 f, 6.3v panasonic sp 1 f 25v 180 f, 4v panasonic sp gnd on/off 8 5 1 2 3 v out2 3.3v 5a; 6a peak v out3 12v 120ma 33 f 25v v out1 5v 3a; 4a peak v in 7v to 28v 1628 f12 + + v in : 7v to 28v v out : 5v, 3a/3.3v, 6a/12v, 120ma switching frequency = 300khz mi, m2, m3, m4: nds8410a l1: sumida cep123-6r3mc t1: 10 h 1:1.8 ?dale lpe6562-a262 gapped e-core or bh electronics #501-0657 gapped toroid lt1121 + + 220k 100k 1m pgood 100k v pull-up (<7v) 59k 180pf 180pf 0.01 f u typical applicatio
31 LTC3707 3707f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. u package descriptio 0.386 ?0.393* (9.804 ?9.982) gn28 (ssop) 1098 * dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side 12 3 4 5 6 7 8 9 10 11 12 0.229 ?0.244 (5.817 ?6.198) 0.150 ?0.157** (3.810 ?3.988) 20 21 22 23 24 25 26 27 28 19 18 17 13 14 16 15 0.016 ?0.050 (0.406 ?1.270) 0.015 0.004 (0.38 0.10) 45 0 ?8 typ 0.0075 ?0.0098 (0.191 ?0.249) 0.053 ?0.069 (1.351 ?1.748) 0.008 ?0.012 (0.203 ?0.305) 0.004 ?0.009 (0.102 ?0.249) 0.0250 (0.635) bsc 0.033 (0.838) ref gn package 28-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641)
32 LTC3707 3707f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com ? linear technology corporation 2001 lt/tp 1101 1k ? printed in usa figure 13. LTC3707 5v/4a, 3.3v/4a regulator related parts part number description comments ltc1159 high efficiency synchronous step-down switching regulator 100% dc, logic level mosfets, v in < 40v ltc1438/ltc1439 dual high efficiency low noise synchronous step-down switching regulators por, auxiliary regulator ltc1438-adj dual synchronous controller with auxiliary regulator por, external feedback divider ltc1538-aux dual high efficiency low noise synchronous step-down switching regulator auxiliary regulator, 5v standby ltc1539 dual high efficiency low noise synchronous step-down switching regulator 5v standby, por, low-battery, aux regulator ltc1530 high power step-down synchronous dc/dc controller in so-8 high efficiency 5v to 3.3v conversion at up to 15a ltc1625/ltc1775 no r sense tm current mode synchronous step-down controller 97% efficiency, no sense resistor, 16-pin ssop ltc1628/ltc1628-pg dual high efficiency 2-phase synchronous step-down switching regulator constant frequency, 5v and 3.3v ldos, v in 36v ltc1629 20a to 200a polyphase tm synchronous controller expandable from 2-phase to 12-phase, uses all surface mount components, no heat sink ltc1702 no r sense 2-phase dual synchronous step-down controller 550khz, no sense resistor ltc1703 no r sense 2-phase dual synchronous step-down controller mobile pentium ? iii processors, 550khz, with 5-bit mobile vid control v in 7v lt1709 high efficiency, 2-phase synchronous step-down switching regulator 1.3v v out 3.5v, current mode ensures with 5-bit vid accurate current sharing, 3.5v v in 36v ltc1735 high efficiency synchronous step-down switching regulator output fault protection, 16-pin ssop ltc1736 high efficiency synchronous controller with 5-bit mobile vid control output fault protection, 24-pin ssop, 3.5v v in 36v ltc1929 2-phase synchronous controller up to 42a, uses all surface mount components, no heat sink, 3.5v v in 36v adaptive power, no r sense and polyphase are trademarks of linear technology corporation. pentium is a registered trademark of intel corporation. 0.1 f 4.7 f 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 + 22 f 50v m1a m1b m2a m2b 1 f 10v 0.1 f 10 0.015 0.015 intv cc 3.3v 0.1 f 20k 1% 105k 1% 33pf 15k 33pf 15k 220pf 220pf 1000pf 1000pf 0.1 f 20k 1% 63.4k 1% run/ss1 sense1 + sense1 v osense1 freqset stbymd fcb i th1 sgnd 3.3v out i th2 v osense2 sense2 sense2 + pgood tg1 sw1 boost1 v in bg1 extv cc intv cc pgnd bg2 boost2 sw2 tg2 run/ss2 LTC3707 l1 8 h l2 8 h 47 f 6.3v 56 f, 4v gnd v out2 3.3v 3a; 4a peak v out1 5v 3a; 4a peak v in 5.2v to 28v 3707 f13 + + v in : 5.2v to 28v v out : 5v, 4a/3.3v, 4a switching frequency = 300khz mi, m2: fds6982s l1, l2: 8 h sumida cep1238r0mc output capacitors: panasonic sp series 27pf 27pf 0.1 f cmdsh-3tr cmdsh-3tr 0.01 f pgood v pull-up (<7v) u typical applicatio

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